The present invention relates to integrated circuit devices and, more particularly, to methods and apparatus for saving power in digital integrated circuits when driving complementary data lines.
Many digital integrated circuit devices include pairs of complementary data lines that provide differential digital data signals to and from circuits and devices therein. In integrated circuit memory devices, these complementary data lines may take the form of a plurality of pairs of complementary bit lines (e.g., BIT, /BIT) that are electrically coupled to respective columns of memory cells within a memory cell array. Conventional techniques for switching data signals on pairs of complementary bit lines typically include using complementary drivers to actively pull one of the bit lines within a pair up from a logic 0 voltage to a full logic 1 voltage while simultaneously pulling the other bit line within the pair down from a logic 1 voltage to a logic 0 voltage. If the switching losses associated with the complementary drivers are ignored, then each switching event that causes BIT to switch low-to-high and /BIT to switch high-to-low, or vice versa, typically draws a charge of C(xcex94VBIT) coulombs from the power supply, where C represents the capacitance of a bit line and xcex94VBIT (or xcex94V/BIT) represents the voltage swing associated with pulling the true or complementary bit line from a logic 0 voltage to a logic 1 voltage. Assuming xcex94VBIT equals a power supply potential of Vdd, then the expression for charge required can be simplified to CVdd coulombs for each high-to-low and low-to-high switching event pair. A different expression may apply in the event the logic 0 voltage and the logic 1 voltage do not equal 0 volts and Vdd, respectively.
However, for many applications requiring reduced power consumption, including those having battery powered supplies and those in which total power consumption requires special heat dissipating packaging, the energy associated with drawing this charge from the power supply per switching event for each pair of data lines undergoing a data change is excessive. Accordingly, integrated circuit devices that can provide a full voltage swing across complementary data lines and have reduced power consumption requirements are desirable.
Memory devices and complementary data line driver circuits according to embodiments of the present invention conserve power by evaluating old data on complementary data lines and providing conditional charge recycling in the event the new data to be provided to the complementary data lines differs from the old data residing thereon. One preferred embodiment of a data line driver circuit includes first and second data lines within a complementary data line pair and a driver control circuit that is electrically coupled to the data line pair. The driver control circuit compares the old data on the data line pair to new data to be provided to the data line pair. Based on the comparison and a determination that the old data is opposite the new data, the driver control circuit switches the old data to the new data by first transferring charge from the more positively biased one of the first and second data lines to the other data line in the data line pair. The more positively biased one of the first and second data lines may initially be at a logic 1 voltage (e.g., Vdd) and the other data line in the pair may initially be at a logic 0 voltage (e.g., GND). After the charge transfer, both are approximately at xc2xd Vdd. In this manner, at least a portion of the total charge required to pull a data line from a logic 0 voltage to a logic 1 voltage (complementary data line from a logic 1 voltage to a logic 0 voltage) may be provided by an already charged (discharged) complementary data line (true data line), prior to actively pulling the data line high (complementary data line) low to complete the switching process.
According to a preferred aspect of this embodiment, the charge is transferred for a sufficient duration to substantially equilibrate voltages on the first and second data lines. In particular, if the first and second data lines are biased at Vdd and GND, respectively, the duration of the charge transfer may be sufficient to establish respective voltages in a neighborhood of about xc2xd Vdd on the first and second data lines. The first and second data lines are then driven with the new data at the completion of the power saving charge transfer. Alternatively, if the comparison results in a determination that the old data and the new data are the same, then the driver control circuit drives the first and second data lines with the old data and then the new data without interruption and without wasting power by transferring charge unnecessarily from the more positively biased one of the first and second data lines (retaining the old data) to the other data line in the data line pair.
According to another embodiment of the present invention, the driver control circuit may include a equalization transistor having a first current carrying terminal electrically coupled to the first data line and a second current carrying terminal electrically coupled to the second data line. This equalization transistor can provide a direct charge transfer path between the first and second data lines. The driver control circuit drives a gate of the equalization transistor with a turn-on voltage when charge is to be transferred and thereby recycled from one data line to the other in the pair. The driver control circuit may also include a latch that retains the old data while charge is being transferred from the more positively biased one of the first and second data lines. The driver control circuit may evaluate the old data retained by the latch against the new data when determining whether to initiate and continue charge transfer between the data lines. The old data on the latch is replaced with the new data only after the charge transfer process (if. required) is substantially complete. In particular, the operation of driving the first and second data lines from the midpoint to full rail-to-rail signal levels with the new data may be performed in-sync with switching the old data retained by the latch to the new data.
According to still a further aspect of this embodiment, the driver control circuit may include a true data line driver having a first output electrically connected to the first data line and a PMOS pull-up transistor therein. The PMOS pull-up transistor may have a drain electrically connected to the first output, a source electrically connected to a positive power supply line and a gate that receives a first active low signal equal to DATAINB+QB, where DATAIN and DATAINB are complementary signals that represent the new data, Q and QB are complementary signals that represent the old data retained by the latch, and xe2x80x9c+xe2x80x9d designates an OR operator. Accordingly, the PMOS pull-up transistor associated with the true data line driver will only be conductive (requiring the PMOS gate to be low) if the new data DATAIN=1 and the old data Q=1. A complementary data line driver is also provided that has a second output electrically connected to the second data line and a PMOS pull-up transistor having a drain electrically connected to the second output, a source electrically connected to the power supply line and a gate that receives a second signal equal to DATAIN+Q. Accordingly, the PMOS pull-up transistor associated with the complementary data line driver will only be conductive if the new data DATAIN=0 and the old data Q=0.
The true data line driver also includes a NMOS pull-down transistor having a drain electrically connected to the first output, a source electrically connected to a ground reference line and a gate that receives a signal equal to DATABINxc3x97QB, where xe2x80x9cxxe2x80x9d designates an AND operator. Similarly, the complementary data line driver includes an NMOS pull-down transistor having a drain electrically connected to the second output, a source electrically connected to the ground reference line and a gate that receives a second signal equal to DATAINxc3x97Q. The driver control circuit is also configured to provide the gate of an NMOS equalization transistor with a signal equal to (DATAIN⊕Q), where xe2x80x9c⊕xe2x80x9d designates an exclusive OR operator.
According to another embodiment of the present invention, a preferred data line driver circuit includes first and second data lines within a complementary data line pair and a driver control circuit that is electrically coupled to the data line pair and performs a comparison of old data on the data line pair to new data to be provided to the data line pair. Based on this comparison and a determination that the old data is opposite the new data, the driver control circuit switches the old data to the new data by first transferring a quantity of charge Q that is greater than about 0.15CVdata from a more positively biased one of the first and second data lines to the other data line in the data line pair, where C is a capacitance of the more positively biased one of the first and second data lines and Vdata is a voltage of the more positively biased one of the first and second data lines relative to the other one the first and second data lines at a commencement of transferring the charge Q. More preferably, the duration of the charge transfer is sufficient to transfer enough charge Q that the voltages on the first and second data lines are equilibrated to within about 0.2Vdata.
According to still another embodiment of the present invention, an integrated circuit memory device includes an Nxc3x97M array of data storage cells arranged as N rows of data storage cells and M columns of data storage cells. These storage cells may include, but are not limited to, memory cells such as static random access memory (SRAM) cells and content addressable memory (CAM) cells. A plurality of pairs of complementary data lines (e.g., BIT, /BIT and DATA, /DATA in a CAM) are electrically coupled to the columns of data storage cells and an integrated data line driver control circuit is electrically coupled to the plurality of pairs of complementary data lines. Many of the following examples will assume that data lines are used as bit lines in a memory device, whether they be global data lines or data lines in a CAM containing the data to be located, for example. The integrated bit line driver control circuit includes a plurality of bit line driver control cells, with each cell being electrically coupled to first and second bit lines within one of the plurality of pairs of complementary bit lines. A bit line driver control cell performs a comparison of old data on the first and second bit lines and new data to be provided to the first and second bit lines. Based on that comparison and a determination that the new data is opposite the old data, the bit line driver control cell first transfers charge from a more positively biased one of the first and second bit lines to the other bit line in the bit line pair and then, after a sufficient amount of charge has been transferred and recycled, terminates the charge transfer between the bit lines and actively drives the first and second bit lines with the new data. A sufficient amount of charge is preferably that amount of charge necessary to substantially equilibrate voltages on the first and second bit lines.
Still further embodiments of the present invention include methods of operating integrated circuit memory devices by driving first and second bit lines within a complementary bit line pair with first data that causes the first bit line to become more positively biased than the second bit line, during a first time interval. Then, upon application of second new data that is opposite the first data, the first and second bit lines are driven with new data in two steps, first by transferring charge from the first bit line to the second bit line during a leading portion of a second time interval that commences upon termination of the first time interval. This charge transfer may be enabled by turning on an equalization transistor having first and second current carrying terminals that are electrically connected to the first and second bit lines. Then, after charge transferring is substantially complete (i.e., the voltages of the complementary bit lines are nearly equal), the charge transfer path is disabled after which the complementary bit lines are driven to their full logic levels.
In the above method, the step of driving the first and second bit lines with second opposite data includes turning on the equalization transistor and transferring charge from the first bit line to the second bit line during the leading portion of the second time interval while the outputs of the first and second bit line driver devices are maintained in high-impedance states. Then, upon completion of the charge transfer, the equalization transistor is turned off and the first and second bit lines are driven with the new data by pulling down the first bit line with the first bit line driver and pulling up the second bit line with the second bit line driver during a trailing portion of the second time interval. Although less preferred from a power savings standpoints, the first and second bit line drivers may be active during the leading portion of the second time interval.